`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/08/27 15:44:26
// Design Name: 
// Module Name: sim_tri_and_gate
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sim_tri_and_gate(
    );
reg clk;  
reg A;
reg B;
wire Y;
tri_and_gate u1(clk,A,B,Y);
initial 
begin
    clk=1'b0;A=1'b0;B=1'b0;
    #100 A=1'b0;B=1'b1;
    #100 A=1'b1;B=1'b1;
    #100 A=1'b1;B=1'b0;
    #100 A=1'b0;B=1'b0;
end
always
begin
    #10
    clk=~clk;
end
endmodule
